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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-12 15:39:40 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-12 17:39:13 +0200 |
| commit | 240351c44ecadc3a5c67b298568a04373883eca5 (patch) | |
| tree | 49005db55bf1e757176ea470d99b7b5c3509ed9e /passes/techmap/dfflegalize.cc | |
| parent | eef0ec6aed782363c833cd378a158ca60d9d9314 (diff) | |
| download | yosys-240351c44ecadc3a5c67b298568a04373883eca5.tar.gz yosys-240351c44ecadc3a5c67b298568a04373883eca5.tar.bz2 yosys-240351c44ecadc3a5c67b298568a04373883eca5.zip | |
dfflegalize: Gather init values from all wires.
Skipping non-selected wires is unsound in an obvious way.
Diffstat (limited to 'passes/techmap/dfflegalize.cc')
| -rw-r--r-- | passes/techmap/dfflegalize.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index c0f112836..13ce4f49a 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -1296,7 +1296,7 @@ unrecognized: sigmap.set(module); initbits.clear(); - for (auto wire : module->selected_wires()) + for (auto wire : module->wires()) { if (wire->attributes.count(ID::init) == 0) continue; |