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authorEddie Hung <eddie@fpgeh.com>2019-08-15 10:05:08 -0700
committerEddie Hung <eddie@fpgeh.com>2019-08-15 10:05:08 -0700
commit9f98241010481588d643c6d4e24d7b9af2b37c2f (patch)
tree234a3d4424286615e8afa2ebba8d693ba2773489 /passes/techmap/dff2dffs.cc
parent4cfefae21e872bb5a4dc13473316352da2b7a916 (diff)
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Transform "$.*" to ID("$.*") in passes/techmap
Diffstat (limited to 'passes/techmap/dff2dffs.cc')
-rw-r--r--passes/techmap/dff2dffs.cc30
1 files changed, 15 insertions, 15 deletions
diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc
index 39a4f6ade..1fe225aa1 100644
--- a/passes/techmap/dff2dffs.cc
+++ b/passes/techmap/dff2dffs.cc
@@ -51,8 +51,8 @@ struct Dff2dffsPass : public Pass {
extra_args(args, argidx, design);
pool<IdString> dff_types;
- dff_types.insert("$_DFF_N_");
- dff_types.insert("$_DFF_P_");
+ dff_types.insert(ID($_DFF_N_));
+ dff_types.insert(ID($_DFF_P_));
for (auto module : design->selected_modules())
{
@@ -69,7 +69,7 @@ struct Dff2dffsPass : public Pass {
continue;
}
- if (cell->type != "$_MUX_")
+ if (cell->type != ID($_MUX_))
continue;
SigBit bit_a = sigmap(cell->getPort("\\A"));
@@ -114,22 +114,22 @@ struct Dff2dffsPass : public Pass {
}
if (sr_val == State::S1) {
- if (cell->type == "$_DFF_N_") {
- if (invert_sr) cell->type = "$__DFFS_NN1_";
- else cell->type = "$__DFFS_NP1_";
+ if (cell->type == ID($_DFF_N_)) {
+ if (invert_sr) cell->type = ID($__DFFS_NN1_);
+ else cell->type = ID($__DFFS_NP1_);
} else {
- log_assert(cell->type == "$_DFF_P_");
- if (invert_sr) cell->type = "$__DFFS_PN1_";
- else cell->type = "$__DFFS_PP1_";
+ log_assert(cell->type == ID($_DFF_P_));
+ if (invert_sr) cell->type = ID($__DFFS_PN1_);
+ else cell->type = ID($__DFFS_PP1_);
}
} else {
- if (cell->type == "$_DFF_N_") {
- if (invert_sr) cell->type = "$__DFFS_NN0_";
- else cell->type = "$__DFFS_NP0_";
+ if (cell->type == ID($_DFF_N_)) {
+ if (invert_sr) cell->type = ID($__DFFS_NN0_);
+ else cell->type = ID($__DFFS_NP0_);
} else {
- log_assert(cell->type == "$_DFF_P_");
- if (invert_sr) cell->type = "$__DFFS_PN0_";
- else cell->type = "$__DFFS_PP0_";
+ log_assert(cell->type == ID($_DFF_P_));
+ if (invert_sr) cell->type = ID($__DFFS_PN0_);
+ else cell->type = ID($__DFFS_PP0_);
}
}
cell->setPort("\\R", sr_sig);