Transform all "\\*" identifiers into ID()

1 files changed, 29 insertions, 29 deletions

diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index 044b0a621..9c1ee1845 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -53,7 +53,7 @@ struct Dff2dffeWorker
 
 		for (auto cell : module->cells()) {
 			if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) {
-				RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
+				RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID(\\Y)));
 				for (int i = 0; i < GetSize(sig_y); i++)
 					bit2mux[sig_y[i]] = cell_int_t(cell, i);
 			}
@@ -86,9 +86,9 @@ struct Dff2dffeWorker
 			return ret;
 
 		cell_int_t mux_cell_int = bit2mux.at(d);
-		RTLIL::SigSpec sig_a = sigmap(mux_cell_int.first->getPort("\\A"));
-		RTLIL::SigSpec sig_b = sigmap(mux_cell_int.first->getPort("\\B"));
-		RTLIL::SigSpec sig_s = sigmap(mux_cell_int.first->getPort("\\S"));
+		RTLIL::SigSpec sig_a = sigmap(mux_cell_int.first->getPort(ID(\\A)));
+		RTLIL::SigSpec sig_b = sigmap(mux_cell_int.first->getPort(ID(\\B)));
+		RTLIL::SigSpec sig_s = sigmap(mux_cell_int.first->getPort(ID(\\S)));
 		int width = GetSize(sig_a), index = mux_cell_int.second;
 
 		for (int i = 0; i < GetSize(sig_s); i++)
@@ -97,9 +97,9 @@ struct Dff2dffeWorker
 				ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path);
 
 				if (sig_b[i*width + index] == q) {
-					RTLIL::SigSpec s = mux_cell_int.first->getPort("\\B");
+					RTLIL::SigSpec s = mux_cell_int.first->getPort(ID(\\B));
 					s[i*width + index] = RTLIL::Sx;
-					mux_cell_int.first->setPort("\\B", s);
+					mux_cell_int.first->setPort(ID(\\B), s);
 				}
 
 				return ret;
@@ -120,9 +120,9 @@ struct Dff2dffeWorker
 				ret.insert(pat);
 
 			if (sig_b[i*width + index] == q) {
-				RTLIL::SigSpec s = mux_cell_int.first->getPort("\\B");
+				RTLIL::SigSpec s = mux_cell_int.first->getPort(ID(\\B));
 				s[i*width + index] = RTLIL::Sx;
-				mux_cell_int.first->setPort("\\B", s);
+				mux_cell_int.first->setPort(ID(\\B), s);
 			}
 		}
 
@@ -130,9 +130,9 @@ struct Dff2dffeWorker
 			ret.insert(pat);
 
 		if (sig_a[index] == q) {
-			RTLIL::SigSpec s = mux_cell_int.first->getPort("\\A");
+			RTLIL::SigSpec s = mux_cell_int.first->getPort(ID(\\A));
 			s[index] = RTLIL::Sx;
-			mux_cell_int.first->setPort("\\A", s);
+			mux_cell_int.first->setPort(ID(\\A), s);
 		}
 
 		return ret;
@@ -185,8 +185,8 @@ struct Dff2dffeWorker
 
 	void handle_dff_cell(RTLIL::Cell *dff_cell)
 	{
-		RTLIL::SigSpec sig_d = sigmap(dff_cell->getPort("\\D"));
-		RTLIL::SigSpec sig_q = sigmap(dff_cell->getPort("\\Q"));
+		RTLIL::SigSpec sig_d = sigmap(dff_cell->getPort(ID(\\D)));
+		RTLIL::SigSpec sig_q = sigmap(dff_cell->getPort(ID(\\Q)));
 
 		std::map<patterns_t, std::set<int>> grouped_patterns;
 		std::set<int> remaining_indices;
@@ -208,15 +208,15 @@ struct Dff2dffeWorker
 			}
 			if (!direct_dict.empty()) {
 				log("  converting %s cell %s to %s for %s -> %s.\n", log_id(dff_cell->type), log_id(dff_cell), log_id(direct_dict.at(dff_cell->type)), log_signal(new_sig_d), log_signal(new_sig_q));
-				dff_cell->setPort("\\E", make_patterns_logic(it.first, true));
+				dff_cell->setPort(ID(\\E), make_patterns_logic(it.first, true));
 				dff_cell->type = direct_dict.at(dff_cell->type);
 			} else
 			if (dff_cell->type == ID($dff)) {
-				RTLIL::Cell *new_cell = module->addDffe(NEW_ID, dff_cell->getPort("\\CLK"), make_patterns_logic(it.first, false),
-						new_sig_d, new_sig_q, dff_cell->getParam("\\CLK_POLARITY").as_bool(), true);
+				RTLIL::Cell *new_cell = module->addDffe(NEW_ID, dff_cell->getPort(ID(\\CLK)), make_patterns_logic(it.first, false),
+						new_sig_d, new_sig_q, dff_cell->getParam(ID(\\CLK_POLARITY)).as_bool(), true);
 				log("  created $dffe cell %s for %s -> %s.\n", log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q));
 			} else {
-				RTLIL::Cell *new_cell = module->addDffeGate(NEW_ID, dff_cell->getPort("\\C"), make_patterns_logic(it.first, true),
+				RTLIL::Cell *new_cell = module->addDffeGate(NEW_ID, dff_cell->getPort(ID(\\C)), make_patterns_logic(it.first, true),
 						new_sig_d, new_sig_q, dff_cell->type == ID($_DFF_P_), true);
 				log("  created %s cell %s for %s -> %s.\n", log_id(new_cell->type), log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q));
 			}
@@ -235,9 +235,9 @@ struct Dff2dffeWorker
 				new_sig_d.append(sig_d[i]);
 				new_sig_q.append(sig_q[i]);
 			}
-			dff_cell->setPort("\\D", new_sig_d);
-			dff_cell->setPort("\\Q", new_sig_q);
-			dff_cell->setParam("\\WIDTH", GetSize(remaining_indices));
+			dff_cell->setPort(ID(\\D), new_sig_d);
+			dff_cell->setPort(ID(\\Q), new_sig_q);
+			dff_cell->setParam(ID(\\WIDTH), GetSize(remaining_indices));
 		}
 	}
 
@@ -361,19 +361,19 @@ struct Dff2dffePass : public Pass {
 								for (auto cell_other : mod->selected_cells()) {
 									if (cell_other->type != cell->type)
 										continue;
-									if (sigmap(cell->getPort("\\EN")) == sigmap(cell_other->getPort("\\EN")))
+									if (sigmap(cell->getPort(ID(\\EN))) == sigmap(cell_other->getPort(ID(\\EN))))
 										ce_use++;
 								}
 								if (ce_use >= min_ce_use)
 									continue;
 							}
 
-							RTLIL::SigSpec tmp = mod->addWire(NEW_ID, GetSize(cell->getPort("\\D")));
-							mod->addDff(NEW_ID, cell->getPort("\\CLK"), tmp, cell->getPort("\\Q"), cell->getParam("\\CLK_POLARITY").as_bool());
-							if (cell->getParam("\\EN_POLARITY").as_bool())
-								mod->addMux(NEW_ID, cell->getPort("\\Q"), cell->getPort("\\D"), cell->getPort("\\EN"), tmp);
+							RTLIL::SigSpec tmp = mod->addWire(NEW_ID, GetSize(cell->getPort(ID(\\D))));
+							mod->addDff(NEW_ID, cell->getPort(ID(\\CLK)), tmp, cell->getPort(ID(\\Q)), cell->getParam(ID(\\CLK_POLARITY)).as_bool());
+							if (cell->getParam(ID(\\EN_POLARITY)).as_bool())
+								mod->addMux(NEW_ID, cell->getPort(ID(\\Q)), cell->getPort(ID(\\D)), cell->getPort(ID(\\EN)), tmp);
 							else
-								mod->addMux(NEW_ID, cell->getPort("\\D"), cell->getPort("\\Q"), cell->getPort("\\EN"), tmp);
+								mod->addMux(NEW_ID, cell->getPort(ID(\\D)), cell->getPort(ID(\\Q)), cell->getPort(ID(\\EN)), tmp);
 							mod->remove(cell);
 							continue;
 						}
@@ -383,7 +383,7 @@ struct Dff2dffePass : public Pass {
 								for (auto cell_other : mod->selected_cells()) {
 									if (cell_other->type != cell->type)
 										continue;
-									if (sigmap(cell->getPort("\\E")) == sigmap(cell_other->getPort("\\E")))
+									if (sigmap(cell->getPort(ID(\\E))) == sigmap(cell_other->getPort(ID(\\E))))
 										ce_use++;
 								}
 								if (ce_use >= min_ce_use)
@@ -393,11 +393,11 @@ struct Dff2dffePass : public Pass {
 							bool clk_pol = cell->type.compare(7, 1, "P") == 0;
 							bool en_pol = cell->type.compare(8, 1, "P") == 0;
 							RTLIL::SigSpec tmp = mod->addWire(NEW_ID);
-							mod->addDff(NEW_ID, cell->getPort("\\C"), tmp, cell->getPort("\\Q"), clk_pol);
+							mod->addDff(NEW_ID, cell->getPort(ID(\\C)), tmp, cell->getPort(ID(\\Q)), clk_pol);
 							if (en_pol)
-								mod->addMux(NEW_ID, cell->getPort("\\Q"), cell->getPort("\\D"), cell->getPort("\\E"), tmp);
+								mod->addMux(NEW_ID, cell->getPort(ID(\\Q)), cell->getPort(ID(\\D)), cell->getPort(ID(\\E)), tmp);
 							else
-								mod->addMux(NEW_ID, cell->getPort("\\D"), cell->getPort("\\Q"), cell->getPort("\\E"), tmp);
+								mod->addMux(NEW_ID, cell->getPort(ID(\\D)), cell->getPort(ID(\\Q)), cell->getPort(ID(\\E)), tmp);
 							mod->remove(cell);
 							continue;
 						}