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| author | Clifford Wolf <clifford@clifford.at> | 2016-10-16 20:37:02 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-10-16 20:37:02 +0200 |
| commit | 74702b04c2775b062aa89b8a4704cd9135d2b048 (patch) | |
| tree | 0b5f839506e44e3a31649cb5086663e69a218359 /passes/techmap/attrmvcp.cc | |
| parent | fa535c0b0041621d0128087cd0236cfd5eb36e48 (diff) | |
| download | yosys-74702b04c2775b062aa89b8a4704cd9135d2b048.tar.gz yosys-74702b04c2775b062aa89b8a4704cd9135d2b048.tar.bz2 yosys-74702b04c2775b062aa89b8a4704cd9135d2b048.zip | |
Build fixes for VS 2015
Diffstat (limited to 'passes/techmap/attrmvcp.cc')
| -rw-r--r-- | passes/techmap/attrmvcp.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/techmap/attrmvcp.cc b/passes/techmap/attrmvcp.cc index 50eaf61df..1537def00 100644 --- a/passes/techmap/attrmvcp.cc +++ b/passes/techmap/attrmvcp.cc @@ -93,6 +93,7 @@ struct AttrmvcpPass : public Pass { for (auto cell : module->selected_cells()) for (auto &conn : cell->connections()) + { if (driven_mode) { if (cell->input(conn.first)) for (auto bit : sigmap(conn.second)) @@ -102,6 +103,7 @@ struct AttrmvcpPass : public Pass { for (auto bit : sigmap(conn.second)) net2cells[bit].insert(cell); } + } for (auto wire : module->selected_wires()) { |