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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-02-23 07:19:52 +0000 |
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| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-02-23 07:22:26 +0000 |
| commit | f0afd65035fefebdea8edbd00c916c5f33e8a634 (patch) | |
| tree | 5d34c5920dc230388c41bb7380e1241dec274fcf /passes/techmap/attrmap.cc | |
| parent | 6edca05793197a846bbfb0329e836c87fa5aabb6 (diff) | |
| download | yosys-f0afd65035fefebdea8edbd00c916c5f33e8a634.tar.gz yosys-f0afd65035fefebdea8edbd00c916c5f33e8a634.tar.bz2 yosys-f0afd65035fefebdea8edbd00c916c5f33e8a634.zip | |
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
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