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author | Clifford Wolf <clifford@clifford.at> | 2015-10-25 19:30:49 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-10-25 19:30:49 +0100 |
commit | 207736b4ee0363ff6714071e64024965916eafc2 (patch) | |
tree | 31092cfab4323500bc491d8b59deee9e297730d0 /passes/techmap/alumacc.cc | |
parent | da923c198e770806a4abb749acc75fa337247920 (diff) | |
download | yosys-207736b4ee0363ff6714071e64024965916eafc2.tar.gz yosys-207736b4ee0363ff6714071e64024965916eafc2.tar.bz2 yosys-207736b4ee0363ff6714071e64024965916eafc2.zip |
Import more std:: stuff into Yosys namespace
Diffstat (limited to 'passes/techmap/alumacc.cc')
-rw-r--r-- | passes/techmap/alumacc.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index 90563c863..3c7ff4b92 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -40,7 +40,7 @@ struct AlumaccWorker { std::vector<RTLIL::Cell*> cells; RTLIL::SigSpec a, b, c, y; - std::vector<std::tuple<bool, bool, bool, bool, RTLIL::SigSpec>> cmp; + std::vector<tuple<bool, bool, bool, bool, RTLIL::SigSpec>> cmp; bool is_signed, invert_b; RTLIL::Cell *alu_cell; @@ -138,7 +138,7 @@ struct AlumaccWorker n->users = 0; for (auto bit : n->y) - n->users = std::max(n->users, bit_users.at(bit) - 1); + n->users = max(n->users, bit_users.at(bit) - 1); if (cell->type.in("$pos", "$neg")) { @@ -409,7 +409,7 @@ struct AlumaccWorker n->a = A; n->b = B; n->c = RTLIL::S1; - n->y = module->addWire(NEW_ID, std::max(GetSize(A), GetSize(B))); + n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B))); n->is_signed = is_signed; n->invert_b = true; sig_alu[RTLIL::SigSig(A, B)].insert(n); |