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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 23:33:37 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 23:33:37 -0800 |
| commit | b678b15c6d0d14580ca18e89f86926eabf8fead0 (patch) | |
| tree | ef79abc9952c2ae0aec32a60ef0ced0549b31768 /passes/techmap/abc9_ops.cc | |
| parent | eb7dd7d3741983fafe62b13c4a2d6a21ced06133 (diff) | |
| download | yosys-b678b15c6d0d14580ca18e89f86926eabf8fead0.tar.gz yosys-b678b15c6d0d14580ca18e89f86926eabf8fead0.tar.bz2 yosys-b678b15c6d0d14580ca18e89f86926eabf8fead0.zip | |
abc9_ops: ignore inouts of all cell outputs for topo ordering
Diffstat (limited to 'passes/techmap/abc9_ops.cc')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 4da10d94b..d7ebfdf3f 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -488,7 +488,9 @@ void reintegrate(RTLIL::Module *module) RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A); RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y); bit_users[a_bit].insert(mapped_cell->name); - bit_drivers[y_bit].insert(mapped_cell->name); + // Ignore inouts for topo ordering + if (y_bit.wire && !(y_bit.wire->port_input && y_bit.wire->port_output)) + bit_drivers[y_bit].insert(mapped_cell->name); if (!a_bit.wire) { mapped_cell->setPort(ID::Y, module->addWire(NEW_ID)); @@ -598,7 +600,9 @@ void reintegrate(RTLIL::Module *module) for (const auto &i : inputs) bit_users[i].insert(mapped_cell->name); for (const auto &i : outputs) - bit_drivers[i].insert(mapped_cell->name); + // Ignore inouts for topo ordering + if (i.wire && !(i.wire->port_input && i.wire->port_output)) + bit_drivers[i].insert(mapped_cell->name); } int input_count = 0, output_count = 0; |