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author | Eddie Hung <eddie@fpgeh.com> | 2020-01-05 10:20:24 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-05 10:20:24 -0800 |
commit | b5f60e055d07579a2d4f23fc053ca030f103f377 (patch) | |
tree | 2a32b253a9a004c47b0e61ca0449a4e93eff40d4 /passes/techmap/abc9_ops.cc | |
parent | 8293a3fe749701c7df425acd81e24a2a34f5032e (diff) | |
download | yosys-b5f60e055d07579a2d4f23fc053ca030f103f377.tar.gz yosys-b5f60e055d07579a2d4f23fc053ca030f103f377.tar.bz2 yosys-b5f60e055d07579a2d4f23fc053ca030f103f377.zip |
write_xaiger to pad, not abc9_ops -prep_holes
Diffstat (limited to 'passes/techmap/abc9_ops.cc')
-rw-r--r-- | passes/techmap/abc9_ops.cc | 39 |
1 files changed, 0 insertions, 39 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index ab5aa9f8d..730431ebf 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -254,45 +254,6 @@ void prep_holes(RTLIL::Module *module, bool dff) RTLIL::Module* box_module = design->module(cell->type); if (!box_module || !box_module->attributes.count("\\abc9_box_id")) continue; - - bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */); - - // Fully pad all unused input connections of this box cell with S0 - // Fully pad all undriven output connections of this box cell with anonymous wires - for (const auto &port_name : box_module->ports) { - RTLIL::Wire* w = box_module->wire(port_name); - log_assert(w); - auto it = cell->connections_.find(port_name); - if (w->port_input) { - RTLIL::SigSpec rhs; - if (it != cell->connections_.end()) { - if (GetSize(it->second) < GetSize(w)) - it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second))); - rhs = it->second; - } - else { - rhs = RTLIL::SigSpec(State::S0, GetSize(w)); - cell->setPort(port_name, rhs); - } - } - if (w->port_output) { - RTLIL::SigSpec rhs; - auto it = cell->connections_.find(w->name); - if (it != cell->connections_.end()) { - if (GetSize(it->second) < GetSize(w)) - it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second))); - rhs = it->second; - } - else { - Wire *wire = module->addWire(NEW_ID, GetSize(w)); - if (blackbox) - wire->set_bool_attribute(ID(abc9_padding)); - rhs = wire; - cell->setPort(port_name, rhs); - } - } - } - cell->attributes["\\abc9_box_seq"] = box_list.size(); box_list.emplace_back(cell); } |