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author | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 21:45:27 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 21:45:27 -0800 |
commit | 2c65e1abacc4401c4fd3e9b48f52c4de120bc511 (patch) | |
tree | c6c70b415aa68e971292462e1b71f11a4bc89736 /passes/techmap/abc9_ops.cc | |
parent | a2c4d98da70744253ccbe253083ef9df5fa39305 (diff) | |
download | yosys-2c65e1abacc4401c4fd3e9b48f52c4de120bc511.tar.gz yosys-2c65e1abacc4401c4fd3e9b48f52c4de120bc511.tar.bz2 yosys-2c65e1abacc4401c4fd3e9b48f52c4de120bc511.zip |
abc9: break SCC by setting (* keep *) on output wires
Diffstat (limited to 'passes/techmap/abc9_ops.cc')
-rw-r--r-- | passes/techmap/abc9_ops.cc | 29 |
1 files changed, 4 insertions, 25 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 9cc58c99d..4da10d94b 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -53,30 +53,7 @@ void break_scc(RTLIL::Module *module) if (cell->output(c.first)) { SigBit b = c.second.as_bit(); Wire *w = b.wire; - if (w->port_input) { - // In this case, hopefully the loop break has been already created - // Get the non-prefixed wire - Wire *wo = module->wire(stringf("%s.abco", b.wire->name.c_str())); - log_assert(wo != nullptr); - log_assert(wo->port_output); - log_assert(b.offset < GetSize(wo)); - c.second = RTLIL::SigBit(wo, b.offset); - } - else { - // Create a new output/input loop break - w->port_input = true; - w = module->wire(stringf("%s.abco", w->name.c_str())); - if (!w) { - w = module->addWire(stringf("%s.abco", b.wire->name.c_str()), GetSize(b.wire)); - w->port_output = true; - } - else { - log_assert(w->port_input); - log_assert(b.offset < GetSize(w)); - } - w->set_bool_attribute(ID(abc9_scc_break)); - c.second = RTLIL::SigBit(w, b.offset); - } + w->set_bool_attribute(ID::keep); } } } @@ -586,7 +563,9 @@ void reintegrate(RTLIL::Module *module) } if (cell->output(mapped_conn.first)) for (auto i : mapped_conn.second) - bit_drivers[i].insert(mapped_cell->name); + // Ignore inouts for topo ordering + if (i.wire && !(i.wire->port_input && i.wire->port_output)) + bit_drivers[i].insert(mapped_cell->name); } } else { |