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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 18:46:22 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 18:46:22 -0800 |
| commit | 0317a2b476f5ec78cab35b79a02d166c84c0f53e (patch) | |
| tree | 9dcb241bb8f4aa5a25c56cdf453549f55c633024 /passes/techmap/abc9_ops.cc | |
| parent | 65baefecd39b3be641b9a6be350d2ae83854cacc (diff) | |
| download | yosys-0317a2b476f5ec78cab35b79a02d166c84c0f53e.tar.gz yosys-0317a2b476f5ec78cab35b79a02d166c84c0f53e.tar.bz2 yosys-0317a2b476f5ec78cab35b79a02d166c84c0f53e.zip | |
holes_module to be whitebox
Diffstat (limited to 'passes/techmap/abc9_ops.cc')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 8eb935e1f..e65b16fc6 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -434,6 +434,8 @@ void prep_holes(RTLIL::Module *module) holes_design->modules_.erase(holes_module->name); holes_module->design = design; + holes_module->set_bool_attribute(ID::whitebox); + log_pop(); } @@ -480,6 +482,14 @@ struct Abc9PrepPass : public Pass { extra_args(args, argidx, design); for (auto mod : design->selected_modules()) { + if (mod->get_blackbox_attribute()) + continue; + + if (mod->processes.size() > 0) { + log("Skipping module %s as it contains processes.\n", log_id(mod)); + continue; + } + if (break_scc_mode) break_scc(mod); if (unbreak_scc_mode) |