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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 09:43:57 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 09:43:57 -0800 |
| commit | 808b388e34f3cededd450de35555476874cf2799 (patch) | |
| tree | 4e74cdb031ce90d0c5978cd631644b67a2ea1689 /passes/techmap/abc9_exe.cc | |
| parent | 9f3cb981d7c0767f40febf0b32e0a19c28d8e6a0 (diff) | |
| download | yosys-808b388e34f3cededd450de35555476874cf2799.tar.gz yosys-808b388e34f3cededd450de35555476874cf2799.tar.bz2 yosys-808b388e34f3cededd450de35555476874cf2799.zip | |
abc9: log which module is being operated on
Diffstat (limited to 'passes/techmap/abc9_exe.cc')
| -rw-r--r-- | passes/techmap/abc9_exe.cc | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index c1687ef97..a2acfac91 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -168,10 +168,6 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe std::string wire_delay, std::string tempdir_name ) { - //FIXME: - //log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n", - // module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str()); - std::string abc9_script; if (!lut_costs.empty()) |