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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-19 09:56:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-19 09:56:17 -0700 |
| commit | d81a090d89d87837d3e18f9c724fe5c89ddf1f64 (patch) | |
| tree | 414787e8cdd565eaf225c3b0a21c56d8d4134697 /passes/techmap/abc9.cc | |
| parent | 5abe133323b2a6a46959f796c4730b2d70cdea26 (diff) | |
| download | yosys-d81a090d89d87837d3e18f9c724fe5c89ddf1f64.tar.gz yosys-d81a090d89d87837d3e18f9c724fe5c89ddf1f64.tar.bz2 yosys-d81a090d89d87837d3e18f9c724fe5c89ddf1f64.zip | |
Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
Diffstat (limited to 'passes/techmap/abc9.cc')
| -rw-r--r-- | passes/techmap/abc9.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 4cdd392b5..3768786d4 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1088,25 +1088,25 @@ struct Abc9Pass : public Pass { if (w->port_input) { if (w->attributes.count(ID(abc_scc_break))) scc_break_inputs[m->name].insert(p); - if (w->attributes.count(ID(abc_carry_in))) { + if (w->attributes.count(ID(abc_carry))) { if (carry_in) - log_error("Module '%s' contains more than one 'abc_carry_in' port.\n", log_id(m)); + log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m)); carry_in = w; } } if (w->port_output) { - if (w->attributes.count(ID(abc_carry_out))) { + if (w->attributes.count(ID(abc_carry))) { if (carry_out) - log_error("Module '%s' contains more than one 'abc_carry_out' port.\n", log_id(m)); + log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m)); carry_out = w; } } } if (carry_in || carry_out) { if (carry_in && !carry_out) - log_error("Module '%s' contains an 'abc_carry_in' port but no 'abc_carry_out' port.\n", log_id(m)); + log_error("Module '%s' contains an 'abc_carry' input port but no output port.\n", log_id(m)); if (!carry_in && carry_out) - log_error("Module '%s' contains an 'abc_carry_out' port but no 'abc_carry_in' port.\n", log_id(m)); + log_error("Module '%s' contains an 'abc_carry' output port but no input port.\n", log_id(m)); // Make carry_in the last PI, and carry_out the last PO // since ABC requires it this way auto &ports = m->ports; |