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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 11:58:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 11:58:59 -0700 |
| commit | 4cfef7897f4bac285853bf0f08ae366523ae76b4 (patch) | |
| tree | 238a71ec6696966652211fb79bd52c3c8c97eee7 /passes/techmap/abc9.cc | |
| parent | 4486a98fd5928a4e3cdf9cd27c27b7dd821513bb (diff) | |
| parent | eaf3c247729365cec776e147f380ce59f7dccd4d (diff) | |
| download | yosys-4cfef7897f4bac285853bf0f08ae366523ae76b4.tar.gz yosys-4cfef7897f4bac285853bf0f08ae366523ae76b4.tar.bz2 yosys-4cfef7897f4bac285853bf0f08ae366523ae76b4.zip | |
Merge branch 'xaig' into xc7mux
Diffstat (limited to 'passes/techmap/abc9.cc')
| -rw-r--r-- | passes/techmap/abc9.cc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index b14eef485..3cee5a586 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -25,7 +25,8 @@ #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2" -#define ABC_COMMAND_LUT "&st; &fraig; &scorr; &dc2; &retime; &dch -f; &if; &mfs" +//#define ABC_COMMAND_LUT "&st; &sweep; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps" +#define ABC_COMMAND_LUT "&st; &scorr; &dc2; &retime; &dch -f; &if; &ps -l -m" #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}" #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" @@ -343,7 +344,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri else abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str()); - abc_script += stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str()); + abc_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str()); if (!script_file.empty()) { if (script_file[0] == '+') { @@ -1401,6 +1402,9 @@ struct Abc9Pass : public Pass { for (auto mod : design->selected_modules()) { + if (mod->attributes.count("\\abc_box_id")) + continue; + if (mod->processes.size() > 0) { log("Skipping module %s as it contains processes.\n", log_id(mod)); continue; |