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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 14:51:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 14:51:12 -0700 |
| commit | eae5a6b12c0f44230f61ed23068e7200507f9520 (patch) | |
| tree | 51fffae9b283c2310acf18b80ec814f2602ac342 /passes/techmap/abc.cc | |
| parent | 52355f5185fe42e28775e897f458b38a439c0ec5 (diff) | |
| download | yosys-eae5a6b12c0f44230f61ed23068e7200507f9520.tar.gz yosys-eae5a6b12c0f44230f61ed23068e7200507f9520.tar.bz2 yosys-eae5a6b12c0f44230f61ed23068e7200507f9520.zip | |
Use ID::keep more liberally too
Diffstat (limited to 'passes/techmap/abc.cc')
| -rw-r--r-- | passes/techmap/abc.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 205f05ab9..4e49b73ba 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -198,7 +198,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff) if (keepff) for (auto &c : sig_q.chunks()) if (c.wire != NULL) - c.wire->attributes[ID(keep)] = 1; + c.wire->attributes[ID::keep] = 1; assign_map.apply(sig_d); assign_map.apply(sig_q); @@ -787,7 +787,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin extract_cell(c, keepff); for (auto &wire_it : module->wires_) { - if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute(ID(keep))) + if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute(ID::keep)) mark_port(RTLIL::SigSpec(wire_it.second)); } |