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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-22 19:07:55 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-22 19:07:55 -0700 |
| commit | ab11f2aa701f4ff7a8df98d2a4158ea1f661a205 (patch) | |
| tree | d2c8e2b82b7cca57127bd9dd54d3eb40386a88f7 /passes/techmap/abc.cc | |
| parent | d90c1e952256dc00d070863835e061d73e4bc6b3 (diff) | |
| parent | 7311be4028a9caad5a0fac1a3433220b4233ef84 (diff) | |
| download | yosys-ab11f2aa701f4ff7a8df98d2a4158ea1f661a205.tar.gz yosys-ab11f2aa701f4ff7a8df98d2a4158ea1f661a205.tar.bz2 yosys-ab11f2aa701f4ff7a8df98d2a4158ea1f661a205.zip | |
Merge https://github.com/cliffordwolf/yosys
Diffstat (limited to 'passes/techmap/abc.cc')
| -rw-r--r-- | passes/techmap/abc.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index cddc23661..67fef32a2 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -616,7 +616,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin if (!cleanup) tempdir_name[0] = tempdir_name[4] = '_'; tempdir_name = make_temp_dir(tempdir_name); - log_header("Extracting gate netlist of module `%s' to `%s/input.blif'..\n", + log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n", module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str()); std::string abc_script = stringf("read_blif %s/input.blif; ", tempdir_name.c_str()); @@ -834,7 +834,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin if (count_output > 0) { - log_header("Executing ABC.\n"); + log_header(design, "Executing ABC.\n"); buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str()); f = fopen(buffer.c_str(), "wt"); @@ -904,7 +904,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin ifs.close(); - log_header("Re-integrating ABC results.\n"); + log_header(design, "Re-integrating ABC results.\n"); RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"]; if (mapped_mod == NULL) log_error("ABC output file does not contain a module `netlist'.\n"); @@ -1299,7 +1299,7 @@ struct AbcPass : public Pass { } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - log_header("Executing ABC pass (technology mapping using ABC).\n"); + log_header(design, "Executing ABC pass (technology mapping using ABC).\n"); log_push(); #ifdef ABCEXTERNAL @@ -1599,7 +1599,7 @@ struct AbcPass : public Pass { assigned_cells_reverse[cell] = key; } - log_header("Summary of detected clock domains:\n"); + log_header(design, "Summary of detected clock domains:\n"); for (auto &it : assigned_cells) log(" %d cells in clk=%s%s, en=%s%s\n", GetSize(it.second), std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)), |