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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-01 00:36:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-01 00:36:19 +0100 |
| commit | 7fccad92f76ddeee653d5dfec17868e9766a683a (patch) | |
| tree | c85e80d5652780f3b543e5937f6e7c6a1d191778 /passes/submod | |
| parent | cd71c70b4f55c89cdcfd6da23ff5f2002cb7d49d (diff) | |
| download | yosys-7fccad92f76ddeee653d5dfec17868e9766a683a.tar.gz yosys-7fccad92f76ddeee653d5dfec17868e9766a683a.tar.bz2 yosys-7fccad92f76ddeee653d5dfec17868e9766a683a.zip | |
Added more help messages
Diffstat (limited to 'passes/submod')
| -rw-r--r-- | passes/submod/submod.cc | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/passes/submod/submod.cc b/passes/submod/submod.cc index ba1b4b08b..f30e415b3 100644 --- a/passes/submod/submod.cc +++ b/passes/submod/submod.cc @@ -239,7 +239,24 @@ struct SubmodWorker }; struct SubmodPass : public Pass { - SubmodPass() : Pass("submod") { } + SubmodPass() : Pass("submod", "moving part of a module to a new submodle") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" submod [selection]\n"); + log("\n"); + log("This pass identifies all cells with the 'submod' attribute and moves them to\n"); + log("a newly created module. The value of the attribute is used as name for the\n"); + log("cell that replaces the group of cells with the same attribute value.\n"); + log("\n"); + log("This pass can be used to create a design hierarchy in flat design. This can\n"); + log("be useful for analyzing or reverse-engineering a design.\n"); + log("\n"); + log("This pass only operates on completely selected modules with no processes\n"); + log("or memories.\n"); + log("\n"); + } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing SUBMOD pass (moving cells to submodes as requested).\n"); |