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| author | whitequark <whitequark@whitequark.org> | 2020-06-18 23:34:52 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-18 23:34:52 +0000 |
| commit | 7191dd16f9d486fbe107b2c24d1858c8f88329b3 (patch) | |
| tree | 11a32e71b94bc030afc32d3f8d4c8f3d3ada1588 /passes/sat/supercover.cc | |
| parent | dfde1cf1c540d5580d7bc7d24f9f59a004202d60 (diff) | |
| download | yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.tar.gz yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.tar.bz2 yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.zip | |
Use C++11 final/override keywords.
Diffstat (limited to 'passes/sat/supercover.cc')
| -rw-r--r-- | passes/sat/supercover.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/sat/supercover.cc b/passes/sat/supercover.cc index ba44f02d8..aacc044fb 100644 --- a/passes/sat/supercover.cc +++ b/passes/sat/supercover.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct SupercoverPass : public Pass { SupercoverPass() : Pass("supercover", "add hi/lo cover cells for each wire bit") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -35,7 +35,7 @@ struct SupercoverPass : public Pass { log("checking for a hi signal level and one checking for lo level.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { // bool flag_noinit = false; |