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authorMiodrag Milanovic <mmicko@gmail.com>2022-01-31 13:41:02 +0100
committerMiodrag Milanovic <mmicko@gmail.com>2022-01-31 13:41:02 +0100
commiteabd0ff11560e2d22d007a61010ac9231b413d37 (patch)
tree9459d95fc1b75a9e0071585cd52ea14b8975797d /passes/sat/sim.cc
parent26de52fa094f90d5ce7a2766df5a53e6188b4d13 (diff)
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Compare bits when not all are defined
Diffstat (limited to 'passes/sat/sim.cc')
-rw-r--r--passes/sat/sim.cc20
1 files changed, 17 insertions, 3 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index f08a3eb1f..34a56ff40 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -744,14 +744,28 @@ struct SimInstance
if (item.second==0) continue; // Ignore signals not found
Const fst_val = Const::from_string(shared->fst->valueAt(item.second, time));
Const sim_val = get_state(item.first);
+ if (sim_val.size()!=fst_val.size())
+ log_error("Signal '%s' size is different in gold and gate.\n", log_id(item.first));
if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X
- // TODO: check bit by bit
+ for(int i=0;i<fst_val.size();i++) {
+ if (fst_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
+ log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
+ retVal = true;
+ break;
+ }
+ }
} else if (shared->sim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X
- // TODO: check bit by bit
+ for(int i=0;i<sim_val.size();i++) {
+ if (sim_val[i]!=State::Sx && fst_val[i]!=sim_val[i]) {
+ log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
+ retVal = true;
+ break;
+ }
+ }
} else {
if (fst_val!=sim_val) {
+ log_warning("Signal '%s' in file '%s' in simulation '%s'\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
retVal = true;
- log("signal: %s fst: %s sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));
}
}
//log("signal: %s fst: %s sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val));