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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-01-28 14:20:16 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-01-28 14:20:16 +0100 |
| commit | cb12b7c4d8153896b1f798994aed2aa97a41f011 (patch) | |
| tree | e40e9276327ecbd89a628d2759a1e43b934b70e6 /passes/sat/sim.cc | |
| parent | f0f3c81c566778b223ba3c5c0c224d5e09ac983d (diff) | |
| download | yosys-cb12b7c4d8153896b1f798994aed2aa97a41f011.tar.gz yosys-cb12b7c4d8153896b1f798994aed2aa97a41f011.tar.bz2 yosys-cb12b7c4d8153896b1f798994aed2aa97a41f011.zip | |
ignore not found private signals
Diffstat (limited to 'passes/sat/sim.cc')
| -rw-r--r-- | passes/sat/sim.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 0b9a282e1..65f952915 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -161,6 +161,8 @@ struct SimInstance if (shared->fst) { fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); + if (id==0 && wire->name.isPublic()) + log_warning("Unable to found wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)).c_str()); fst_handles[wire] = id; } @@ -728,6 +730,7 @@ struct SimInstance retVal = true; log("signal: %s fst: %s sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val)); } + //log("signal: %s fst: %s sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val)); } } for (auto child : children) |