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authorJannis Harder <me@jix.one>2022-11-07 14:09:33 +0100
committerJannis Harder <me@jix.one>2022-11-07 14:09:33 +0100
commit9b4fba3870d3d32942fe6ea7fe758a9c17304eab (patch)
tree7f8a5d21c52fbef545d0698d42fc0ebbf0db8b6a /passes/sat/sim.cc
parentcff42f0af5953b66760df293bfce5d0f37a8504c (diff)
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sim: Run a comb-only update step to set past values during FST cosim
The previous approach only initialized past_d and past_ad while for FST cosim we also need to initialize the other past values like past_clk, etc. Also to properly initialize them, we need to run a combinational update step in case any of the wires feeding into the FF are private or otherwise not part of the FST.
Diffstat (limited to 'passes/sat/sim.cc')
-rw-r--r--passes/sat/sim.cc23
1 files changed, 11 insertions, 12 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index b68783f20..3ac431223 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -813,18 +813,6 @@ struct SimInstance
std::string v = shared->fst->valueOf(item.second);
did_something |= set_state(item.first, Const::from_string(v));
}
- for (auto &it : ff_database)
- {
- ff_state_t &ff = it.second;
- SigSpec dsig = it.second.data.sig_d;
- Const value = get_state(dsig);
- if (dsig.is_wire()) {
- ff.past_d = value;
- if (ff.data.has_aload)
- ff.past_ad = value;
- did_something |= true;
- }
- }
for (auto cell : module->cells())
{
if (cell->is_mem_cell()) {
@@ -1019,6 +1007,16 @@ struct SimWorker : SimShared
top->update_ph3();
}
+ void initialize_stable_past()
+ {
+ if (debug)
+ log("\n-- ph1 (initialize) --\n");
+ top->update_ph1();
+ if (debug)
+ log("\n-- ph3 (initialize) --\n");
+ top->update_ph3();
+ }
+
void set_inports(pool<IdString> ports, State value)
{
for (auto portname : ports)
@@ -1191,6 +1189,7 @@ struct SimWorker : SimShared
if (initial) {
did_something |= top->setInitState();
+ initialize_stable_past();
initial = false;
}
if (did_something)