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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-22 14:43:18 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-03-22 14:43:18 +0100 |
| commit | 322ab1cd54f4cddba4e9408887ed822c541185f9 (patch) | |
| tree | 7c3e8572f35d373d05e702026091b41d7bdb86b1 /passes/sat/sim.cc | |
| parent | ff3b0c2c4676a9b717929920fa27098c5f9b53e5 (diff) | |
| download | yosys-322ab1cd54f4cddba4e9408887ed822c541185f9.tar.gz yosys-322ab1cd54f4cddba4e9408887ed822c541185f9.tar.bz2 yosys-322ab1cd54f4cddba4e9408887ed822c541185f9.zip | |
Proper SigBit forming in sim
Diffstat (limited to 'passes/sat/sim.cc')
| -rw-r--r-- | passes/sat/sim.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index b56ccb987..8081ffffe 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1708,13 +1708,13 @@ struct AIWWriter : public OutputWriter if (index < w->start_offset || index > w->start_offset + w->width) log_error("Index %d for wire %s is out of range\n", index, log_signal(w)); if (type == "input") { - aiw_inputs[variable] = SigBit(w,index); + aiw_inputs[variable] = SigBit(w,index-w->start_offset); } else if (type == "init") { - aiw_inits[variable] = SigBit(w,index); + aiw_inits[variable] = SigBit(w,index-w->start_offset); } else if (type == "latch") { - aiw_latches[variable] = {SigBit(w,index), false}; + aiw_latches[variable] = {SigBit(w,index-w->start_offset), false}; } else if (type == "invlatch") { - aiw_latches[variable] = {SigBit(w,index), true}; + aiw_latches[variable] = {SigBit(w,index-w->start_offset), true}; } } |