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| author | Claire Xenia Wolf <claire@clairexen.net> | 2022-02-28 10:41:44 +0100 |
|---|---|---|
| committer | Claire Xenia Wolf <claire@clairexen.net> | 2022-02-28 10:41:44 +0100 |
| commit | 1fd3a642c94b642624f05efecff282c195f984d1 (patch) | |
| tree | 3bc994cb12365319e031b1312e83eeef3db79a95 /passes/sat/sim.cc | |
| parent | 9571acc0bf04a42d3df54c9a844cccd1ab3401fa (diff) | |
| download | yosys-1fd3a642c94b642624f05efecff282c195f984d1.tar.gz yosys-1fd3a642c94b642624f05efecff282c195f984d1.tar.bz2 yosys-1fd3a642c94b642624f05efecff282c195f984d1.zip | |
Hotfix in AIGER witness reader state machine
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
Diffstat (limited to 'passes/sat/sim.cc')
| -rw-r--r-- | passes/sat/sim.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 1cd0a0338..57d6182c0 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1225,6 +1225,7 @@ struct SimWorker : SimShared case 2: write_output_header(); top->setState(latches, line); + state = 3; break; default: if (cycle) { |