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author | Clifford Wolf <clifford@clifford.at> | 2014-01-02 16:52:33 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-01-02 16:52:33 +0100 |
commit | 249ef8695a77c266434c1716707cf15c061290ab (patch) | |
tree | 5f319c68fc0ca376b8d47e8329b2db5dede934f9 /passes/sat/sat.cc | |
parent | e501b8e5c79328095b694ee3f4432f3024ffa598 (diff) | |
download | yosys-249ef8695a77c266434c1716707cf15c061290ab.tar.gz yosys-249ef8695a77c266434c1716707cf15c061290ab.tar.bz2 yosys-249ef8695a77c266434c1716707cf15c061290ab.zip |
Major rewrite of "freduce" command
Diffstat (limited to 'passes/sat/sat.cc')
-rw-r--r-- | passes/sat/sat.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 212021997..fef99dfc0 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -61,7 +61,7 @@ struct SatHelper bool gotTimeout; SatHelper(RTLIL::Design *design, RTLIL::Module *module, bool enable_undef) : - design(design), module(module), sigmap(module), ct(design), satgen(&ez, design, &sigmap) + design(design), module(module), sigmap(module), ct(design), satgen(&ez, &sigmap) { this->enable_undef = enable_undef; satgen.model_undef = enable_undef; |