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author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-22 19:07:55 -0700 |
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committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-22 19:07:55 -0700 |
commit | ab11f2aa701f4ff7a8df98d2a4158ea1f661a205 (patch) | |
tree | d2c8e2b82b7cca57127bd9dd54d3eb40386a88f7 /passes/sat/miter.cc | |
parent | d90c1e952256dc00d070863835e061d73e4bc6b3 (diff) | |
parent | 7311be4028a9caad5a0fac1a3433220b4233ef84 (diff) | |
download | yosys-ab11f2aa701f4ff7a8df98d2a4158ea1f661a205.tar.gz yosys-ab11f2aa701f4ff7a8df98d2a4158ea1f661a205.tar.bz2 yosys-ab11f2aa701f4ff7a8df98d2a4158ea1f661a205.zip |
Merge https://github.com/cliffordwolf/yosys
Diffstat (limited to 'passes/sat/miter.cc')
-rw-r--r-- | passes/sat/miter.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index e809425c8..4854e19bf 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -32,7 +32,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL: bool flag_make_assert = false; bool flag_flatten = false; - log_header("Executing MITER pass (creating miter circuit).\n"); + log_header(design, "Executing MITER pass (creating miter circuit).\n"); size_t argidx; for (argidx = 2; argidx < args.size(); argidx++) @@ -264,7 +264,7 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL bool flag_make_outputs = false; bool flag_flatten = false; - log_header("Executing MITER pass (creating miter circuit).\n"); + log_header(design, "Executing MITER pass (creating miter circuit).\n"); size_t argidx; for (argidx = 2; argidx < args.size(); argidx++) |