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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-03-30 18:00:19 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-03-30 18:00:19 +0000 |
| commit | 00544cffab17cbc6e4c7bf1b34cb41b8949e3aa4 (patch) | |
| tree | 33e984dee008510c83022d42bb00ac43013445d0 /passes/sat/expose.cc | |
| parent | 5a0f029e232164041c409454c1f09877e0ee9fdb (diff) | |
| download | yosys-00544cffab17cbc6e4c7bf1b34cb41b8949e3aa4.tar.gz yosys-00544cffab17cbc6e4c7bf1b34cb41b8949e3aa4.tar.bz2 yosys-00544cffab17cbc6e4c7bf1b34cb41b8949e3aa4.zip | |
Remove unused function parameter.
Diffstat (limited to 'passes/sat/expose.cc')
| -rw-r--r-- | passes/sat/expose.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 51971b92c..8fb47f357 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -96,7 +96,7 @@ void find_dff_wires(std::set<RTLIL::IdString> &dff_wires, RTLIL::Module *module) } } -void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Design *design, RTLIL::Module *module) +void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Module *module) { std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info; SigMap sigmap(module); @@ -313,7 +313,7 @@ struct ExposePass : public Pass { for (auto mod : design->selected_modules()) { - create_dff_dq_map(dff_dq_maps[mod], design, mod); + create_dff_dq_map(dff_dq_maps[mod], mod); if (!flag_shared) continue; |