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author | Clifford Wolf <clifford@clifford.at> | 2013-11-06 22:42:07 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-11-06 22:42:07 +0100 |
commit | f485962c5e0866d84e56c7c95ded2cb9c5cba190 (patch) | |
tree | ce5b07265124e02c1ee430db5965a3ef17668668 /passes/sat/eval.cc | |
parent | 7fe13faefae1e81ce68a399ae09ef396245b4c29 (diff) | |
download | yosys-f485962c5e0866d84e56c7c95ded2cb9c5cba190.tar.gz yosys-f485962c5e0866d84e56c7c95ded2cb9c5cba190.tar.bz2 yosys-f485962c5e0866d84e56c7c95ded2cb9c5cba190.zip |
Added handling of unconnected/unspecified signals to eval -vloghammer_report
Diffstat (limited to 'passes/sat/eval.cc')
-rw-r--r-- | passes/sat/eval.cc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 26b571e29..d805b3c84 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -177,8 +177,12 @@ struct VlogHammerReporter RTLIL::SigSpec sig(module->wires.at("\\y")); RTLIL::SigSpec undef; - if (!ce.eval(sig, undef)) - log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef)); + while (!ce.eval(sig, undef)) { + // log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef)); + log("Warning: Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name)); + ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.width)); + } + log("++VAL++ %d %s %s #\n", idx, module_name.c_str(), sig.as_const().as_string().c_str()); if (module_name == "rtl") { |