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| author | Clifford Wolf <clifford@clifford.at> | 2014-10-10 16:59:44 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-10-10 17:07:24 +0200 |
| commit | 4569a747f8af3880e23408eb93323afc8088b78b (patch) | |
| tree | 81dcea51020173cd4951e8649f8bd8305e7c2591 /passes/sat/eval.cc | |
| parent | c7f5aab625bb90e766c1852592fdf42c951716c0 (diff) | |
| download | yosys-4569a747f8af3880e23408eb93323afc8088b78b.tar.gz yosys-4569a747f8af3880e23408eb93323afc8088b78b.tar.bz2 yosys-4569a747f8af3880e23408eb93323afc8088b78b.zip | |
Renamed SIZE() to GetSize() because of name collision on Win32
Diffstat (limited to 'passes/sat/eval.cc')
| -rw-r--r-- | passes/sat/eval.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index e58a194ec..875896fcd 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -69,7 +69,7 @@ struct BruteForceEquivChecker log_signal(undef2), log_signal(mod1_inputs), log_signal(inputs)); if (ignore_x_mod1) { - for (int i = 0; i < SIZE(sig1); i++) + for (int i = 0; i < GetSize(sig1); i++) if (sig1[i] == RTLIL::State::Sx) sig2[i] = RTLIL::State::Sx; } @@ -290,7 +290,7 @@ struct VlogHammerReporter } else if (rtl_sig.size() > 0) { if (rtl_sig.size() != sig.size()) log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name)); - for (int i = 0; i < SIZE(sig); i++) + for (int i = 0; i < GetSize(sig); i++) if (rtl_sig[i] == RTLIL::State::Sx) sig[i] = RTLIL::State::Sx; } |