diff options
| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-01 17:44:00 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-01 17:44:00 +0200 |
| commit | 86ce441af63b639fc4455cdb541048add253de49 (patch) | |
| tree | 70c22445c689f27d6c534fef1ce0fe337b876a33 /passes/sat/clk2fflogic.cc | |
| parent | 2ec4af56e6ec83fe320cd7af958020ea56e1d9ab (diff) | |
| download | yosys-86ce441af63b639fc4455cdb541048add253de49.tar.gz yosys-86ce441af63b639fc4455cdb541048add253de49.tar.bz2 yosys-86ce441af63b639fc4455cdb541048add253de49.zip | |
Set init values for wrapped async control signals
Diffstat (limited to 'passes/sat/clk2fflogic.cc')
| -rw-r--r-- | passes/sat/clk2fflogic.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index f37e07a89..bc18bbbd6 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -44,6 +44,7 @@ struct Clk2fflogicPass : public Pass { } SigSpec wrap_async_control(Module *module, SigSpec sig, bool polarity, IdString past_sig_id) { Wire *past_sig = module->addWire(past_sig_id, GetSize(sig)); + past_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S0 : State::S1, GetSize(sig)); module->addFf(NEW_ID, sig, past_sig); if (polarity) sig = module->Or(NEW_ID, sig, past_sig); @@ -56,6 +57,7 @@ struct Clk2fflogicPass : public Pass { } SigSpec wrap_async_control_gate(Module *module, SigSpec sig, bool polarity) { Wire *past_sig = module->addWire(NEW_ID); + past_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S0 : State::S1, GetSize(sig)); module->addFfGate(NEW_ID, sig, past_sig); if (polarity) sig = module->OrGate(NEW_ID, sig, past_sig); |