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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:05:41 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:05:41 -0700 |
| commit | 052060f10906ca859d2313b86800e110bd34b79f (patch) | |
| tree | 356107e4270feb84046b984a98e0874f1436b2d9 /passes/sat/clk2fflogic.cc | |
| parent | 35fd9b04731d3bc944e1471b96668ef0cf7b51f1 (diff) | |
| parent | bb2144ae733f1a2c5e629a8251bfbdcc15559aa4 (diff) | |
| download | yosys-052060f10906ca859d2313b86800e110bd34b79f.tar.gz yosys-052060f10906ca859d2313b86800e110bd34b79f.tar.bz2 yosys-052060f10906ca859d2313b86800e110bd34b79f.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'passes/sat/clk2fflogic.cc')
| -rw-r--r-- | passes/sat/clk2fflogic.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index 49ec795d3..4bb4aa047 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -253,6 +253,13 @@ struct Clk2fflogicPass : public Pass { SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge); Const rstval = cell->parameters["\\ARST_VALUE"]; + Wire *past_arst = module->addWire(NEW_ID); + module->addFf(NEW_ID, arst, past_arst); + if (cell->parameters["\\ARST_POLARITY"].as_bool()) + arst = module->LogicOr(NEW_ID, arst, past_arst); + else + arst = module->LogicAnd(NEW_ID, arst, past_arst); + if (cell->parameters["\\ARST_POLARITY"].as_bool()) module->addMux(NEW_ID, qval, rstval, arst, sig_q); else |