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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-15 18:39:20 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-15 18:39:20 -0700 |
| commit | dca45c0888c44857038bd65b6f51f6d9f67b169f (patch) | |
| tree | e0f3cbeb15e8b69a0177fc081dc1732a250e10f3 /passes/proc | |
| parent | 18a40458588f04bf7a3d30fde8fead95cee00dee (diff) | |
| parent | b3378745fd993f48b8114fb08e5019b34374ee72 (diff) | |
| download | yosys-dca45c0888c44857038bd65b6f51f6d9f67b169f.tar.gz yosys-dca45c0888c44857038bd65b6f51f6d9f67b169f.tar.bz2 yosys-dca45c0888c44857038bd65b6f51f6d9f67b169f.zip | |
Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch
Revert "Recognise default entry in case even if all cases covered (fix for #931)"
Diffstat (limited to 'passes/proc')
| -rw-r--r-- | passes/proc/proc_rmdead.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index d2f8d9ead..7c334e661 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -34,7 +34,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) for (size_t i = 0; i < sw->cases.size(); i++) { - bool is_default = GetSize(sw->cases[i]->compare) == 0 || GetSize(sw->signal) == 0; + bool is_default = GetSize(sw->cases[i]->compare) == 0 && (!pool.empty() || GetSize(sw->signal) == 0); for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) { RTLIL::SigSpec sig = sw->cases[i]->compare[j]; |