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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-13 08:17:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-13 08:17:39 -0700 |
| commit | 432a09af80f7dcba9fd517a001e3a1954c99537e (patch) | |
| tree | 1adf4d0a7cdf929de445b000255dfa8ca23663a5 /passes/proc | |
| parent | b567f03c266b0c44d81a24dde2ed538f1db05d4e (diff) | |
| download | yosys-432a09af80f7dcba9fd517a001e3a1954c99537e.tar.gz yosys-432a09af80f7dcba9fd517a001e3a1954c99537e.tar.bz2 yosys-432a09af80f7dcba9fd517a001e3a1954c99537e.zip | |
kernel: SigSpec use more const& + overloads to prevent implicit SigSpec
Diffstat (limited to 'passes/proc')
| -rw-r--r-- | passes/proc/proc_prune.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc index d4aee9df0..caf938a74 100644 --- a/passes/proc/proc_prune.cc +++ b/passes/proc/proc_prune.cc @@ -93,7 +93,7 @@ struct PruneWorker for (int i = 0; i < GetSize(lhs); i++) { RTLIL::SigBit lhs_bit = lhs[i]; if (lhs_bit.wire && !assigned[lhs_bit]) { - conn.first.append_bit(lhs_bit); + conn.first.append(lhs_bit); conn.second.append(rhs.extract(i)); } } |