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authorwhitequark <whitequark@whitequark.org>2019-08-08 05:28:01 +0000
committerwhitequark <whitequark@whitequark.org>2019-08-08 05:32:35 +0000
commit0b09a347dc0163ee19fd4aaa4d306bc82ce7d6d8 (patch)
treeadef6cc5dea44944c6291b8fad222607ed68e7f9 /passes/proc
parent3414ee1e3fe37d4bf383621542828d4fc8fc987f (diff)
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proc_prune: fix handling of exactly identical assigns.
Before this commit, in a process like: process $proc$bug.v:8$3 assign $foo \bar switch \sel case 1'1 assign $foo 1'1 assign $foo 1'1 case assign $foo 1'0 end end both of the "assign $foo 1'1" would incorrectly be removed. Fixes #1243.
Diffstat (limited to 'passes/proc')
-rw-r--r--passes/proc/proc_prune.cc16
1 files changed, 7 insertions, 9 deletions
diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc
index b47ee79c2..d4aee9df0 100644
--- a/passes/proc/proc_prune.cc
+++ b/passes/proc/proc_prune.cc
@@ -65,8 +65,7 @@ struct PruneWorker
pool<RTLIL::SigBit> sw_assigned = do_switch((*it), assigned, affected);
assigned.insert(sw_assigned.begin(), sw_assigned.end());
}
- pool<RTLIL::SigSig> remove;
- for (auto it = cs->actions.rbegin(); it != cs->actions.rend(); ++it) {
+ for (auto it = cs->actions.rbegin(); it != cs->actions.rend(); ) {
RTLIL::SigSpec lhs = sigmap(it->first);
bool redundant = true;
for (auto &bit : lhs) {
@@ -75,9 +74,10 @@ struct PruneWorker
break;
}
}
+ bool remove = false;
if (redundant) {
removed_count++;
- remove.insert(*it);
+ remove = true;
} else {
if (root) {
bool promotable = true;
@@ -99,7 +99,7 @@ struct PruneWorker
}
promoted_count++;
module->connect(conn);
- remove.insert(*it);
+ remove = true;
}
}
for (auto &bit : lhs)
@@ -109,11 +109,9 @@ struct PruneWorker
if (bit.wire)
affected.insert(bit);
}
- }
- for (auto it = cs->actions.begin(); it != cs->actions.end(); ) {
- if (remove[*it]) {
- it = cs->actions.erase(it);
- } else it++;
+ if (remove)
+ cs->actions.erase((it++).base() - 1);
+ else it++;
}
return assigned;
}