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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-01 00:03:00 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-01 00:03:00 -0700 |
| commit | f277267916b7b1c97fe90576abecde003cc231ab (patch) | |
| tree | 3e76c4069a6f8fa37e0f53f927738ed2a8665589 /passes/proc/proc_rmdead.cc | |
| parent | 736a998a75e12ca83b45b74a79e78fae8ab12d16 (diff) | |
| parent | 25533190818b0fe207be9a4626a9a273a08ae219 (diff) | |
| download | yosys-f277267916b7b1c97fe90576abecde003cc231ab.tar.gz yosys-f277267916b7b1c97fe90576abecde003cc231ab.tar.bz2 yosys-f277267916b7b1c97fe90576abecde003cc231ab.zip | |
Merge https://github.com/cliffordwolf/yosys
Diffstat (limited to 'passes/proc/proc_rmdead.cc')
| -rw-r--r-- | passes/proc/proc_rmdead.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index f60d4b30d..af17e8d38 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -51,8 +51,8 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) counter++; continue; } - if (pool.empty()) - sw->cases[i]->compare.clear(); + // if (pool.empty()) + // sw->cases[i]->compare.clear(); } for (auto switch_it : sw->cases[i]->switches) |