Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc

1 files changed, 6 insertions, 7 deletions

diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc
index d5fbef0d2..fe3532da8 100644
--- a/passes/proc/proc_rmdead.cc
+++ b/passes/proc/proc_rmdead.cc
@@ -23,7 +23,6 @@
 #include <sstream>
 #include <stdlib.h>
 #include <stdio.h>
-#include <assert.h>
 #include <set>
 
 static void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)
@@ -32,7 +31,7 @@ static void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)
 
 	for (size_t i = 0; i < sw->cases.size(); i++)
 	{
-		bool is_default = sw->cases[i]->compare.size() == 0 && !pool.empty();
+		bool is_default = SIZE(sw->cases[i]->compare) == 0 && (!pool.empty() || SIZE(sw->signal) == 0);
 
 		for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) {
 			RTLIL::SigSpec sig = sw->cases[i]->compare[j];
@@ -79,18 +78,18 @@ struct ProcRmdeadPass : public Pass {
 		extra_args(args, 1, design);
 
 		int total_counter = 0;
-		for (auto &mod_it : design->modules) {
-			if (!design->selected(mod_it.second))
+		for (auto mod : design->modules()) {
+			if (!design->selected(mod))
 				continue;
-			for (auto &proc_it : mod_it.second->processes) {
-				if (!design->selected(mod_it.second, proc_it.second))
+			for (auto &proc_it : mod->processes) {
+				if (!design->selected(mod, proc_it.second))
 					continue;
 				int counter = 0;
 				for (auto switch_it : proc_it.second->root_case.switches)
 					proc_rmdead(switch_it, counter);
 				if (counter > 0)
 					log("Removed %d dead cases from process %s in module %s.\n", counter,
-							proc_it.first.c_str(), mod_it.first.c_str());
+							proc_it.first.c_str(), log_id(mod));
 				total_counter += counter;
 			}
 		}