proc_dlatch: Refactor to use FfInitVals.

1 files changed, 8 insertions, 28 deletions

diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc
index 3ed158f37..7b8c05b21 100644
--- a/passes/proc/proc_dlatch.cc
+++ b/passes/proc/proc_dlatch.cc
@@ -19,6 +19,7 @@
 
 #include "kernel/register.h"
 #include "kernel/sigtools.h"
+#include "kernel/ffinit.h"
 #include "kernel/consteval.h"
 #include "kernel/log.h"
 #include <sstream>
@@ -32,15 +33,17 @@ struct proc_dlatch_db_t
 {
 	Module *module;
 	SigMap sigmap;
+	FfInitVals initvals;
 
 	pool<Cell*> generated_dlatches;
 	dict<Cell*, vector<SigBit>> mux_srcbits;
 	dict<SigBit, pair<Cell*, int>> mux_drivers;
 	dict<SigBit, int> sigusers;
-	dict<SigBit, std::pair<State,SigBit>> initbits;
 
 	proc_dlatch_db_t(Module *module) : module(module), sigmap(module)
 	{
+		initvals.set(&sigmap, module);
+
 		for (auto cell : module->cells())
 		{
 			if (cell->type.in(ID($mux), ID($pmux)))
@@ -74,29 +77,6 @@ struct proc_dlatch_db_t
 			if (wire->port_input)
 				for (auto bit : sigmap(wire))
 					sigusers[bit]++;
-			if (wire->attributes.count(ID::init)) {
-				SigSpec wirebits = sigmap(wire);
-				Const initval = wire->attributes.at(ID::init);
-
-				for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
-				{
-					SigBit bit = wirebits[i];
-					State val = initval[i];
-
-					if (val != State::S0 && val != State::S1 && bit.wire != nullptr)
-						continue;
-
-					if (initbits.count(bit)) {
-						if (initbits.at(bit).first != val)
-							log_error("Conflicting init values for signal %s (%s = %s != %s).\n",
-									log_signal(bit), log_signal(SigBit(wire, i)),
-									log_signal(val), log_signal(initbits.at(bit).first));
-						continue;
-					}
-
-					initbits[bit] = std::make_pair(val,SigBit(wire,i));
-				}
-			}
 		}
 	}
 
@@ -420,11 +400,11 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
 			log("No latch inferred for signal `%s.%s' from process `%s.%s'.\n",
 					db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
 		for (auto &bit : lhs) {
-			auto it = db.initbits.find(bit);
-			if (it != db.initbits.end()) {
-				log("Removing init bit %s for non-memory siginal `%s.%s` in process `%s.%s`.\n", log_signal(it->second.first), db.module->name.c_str(), log_signal(bit), db.module->name.c_str(), proc->name.c_str());
-				it->second.second.wire->attributes.at(ID::init)[it->second.second.offset] = State::Sx;
+			State val = db.initvals(bit);
+			if (db.initvals(bit) != State::Sx) {
+				log("Removing init bit %s for non-memory siginal `%s.%s` in process `%s.%s`.\n", log_signal(val), db.module->name.c_str(), log_signal(bit), db.module->name.c_str(), proc->name.c_str());
 			}
+			db.initvals.remove_init(bit);
 		}
 		db.module->connect(lhs, rhs);
 		offset += chunk.width;