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author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-07-24 10:20:46 -0700 |
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committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-07-24 10:20:46 -0700 |
commit | c66b7402c06455535bb43ee65fe20515b5b9c0ee (patch) | |
tree | ad135d83bf75e72b65e3136b4f6746c1f9cafab3 /passes/proc/proc_arst.cc | |
parent | 349c47250a9779bc58634870d2e3facfe95fbff8 (diff) | |
parent | a66f17b6a78af8f6989235f0c72d5548b0560a58 (diff) | |
download | yosys-c66b7402c06455535bb43ee65fe20515b5b9c0ee.tar.gz yosys-c66b7402c06455535bb43ee65fe20515b5b9c0ee.tar.bz2 yosys-c66b7402c06455535bb43ee65fe20515b5b9c0ee.zip |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'passes/proc/proc_arst.cc')
-rw-r--r-- | passes/proc/proc_arst.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index b69eba3f9..d069f152a 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -172,7 +172,7 @@ restart_proc_arst: sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0; } for (auto &action : sync->actions) { - RTLIL::SigSpec rspec = action.second; + RTLIL::SigSpec rspec = assign_map(action.second); RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size()); for (int i = 0; i < GetSize(rspec); i++) if (rspec[i].wire == NULL) |