diff options
| author | Ahmed Irfan <ahmedirfan1983@gmail.com> | 2014-01-03 10:54:54 +0100 |
|---|---|---|
| committer | Ahmed Irfan <ahmedirfan1983@gmail.com> | 2014-01-03 10:54:54 +0100 |
| commit | 06482c046bcab4e2b9603f8954ce0f2fd501a73b (patch) | |
| tree | d160ad05402768e4f468ff0685593b81658e6a5a /passes/proc/proc_arst.cc | |
| parent | 5da334fc2efd66c8a5efde925bb18212c34d0cef (diff) | |
| parent | fb2bf934dc6d2c969906b350c9a1b09a972bfdd7 (diff) | |
| download | yosys-06482c046bcab4e2b9603f8954ce0f2fd501a73b.tar.gz yosys-06482c046bcab4e2b9603f8954ce0f2fd501a73b.tar.bz2 yosys-06482c046bcab4e2b9603f8954ce0f2fd501a73b.zip | |
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
Diffstat (limited to 'passes/proc/proc_arst.cc')
| -rw-r--r-- | passes/proc/proc_arst.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 65dc97bdd..571946573 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -47,7 +47,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp polarity = !polarity; return check_signal(mod, cell->connections["\\A"], ref, polarity); } - if (cell->type == "$eq" && cell->connections["\\Y"] == signal) { + if ((cell->type == "$eq" || cell->type == "$eqx") && cell->connections["\\Y"] == signal) { if (cell->connections["\\A"].is_fully_const()) { if (!cell->connections["\\A"].as_bool()) polarity = !polarity; @@ -59,7 +59,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp return check_signal(mod, cell->connections["\\A"], ref, polarity); } } - if (cell->type == "$ne" && cell->connections["\\Y"] == signal) { + if ((cell->type == "$ne" || cell->type == "$nex") && cell->connections["\\Y"] == signal) { if (cell->connections["\\A"].is_fully_const()) { if (cell->connections["\\A"].as_bool()) polarity = !polarity; |