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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 18:08:46 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 18:08:46 -0700 |
| commit | c83a66755553f47f40c591110e6bdcd722360d6c (patch) | |
| tree | e79b8804b52f48cfff77fb0a65f784cb9b6bd341 /passes/pmgen | |
| parent | 2f98f9deee063de1e6a57437f1fe885d42916e19 (diff) | |
| download | yosys-c83a66755553f47f40c591110e6bdcd722360d6c.tar.gz yosys-c83a66755553f47f40c591110e6bdcd722360d6c.tar.bz2 yosys-c83a66755553f47f40c591110e6bdcd722360d6c.zip | |
Fix width of D
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 3cfaa9371..adc09a6e4 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -48,7 +48,7 @@ static Cell* addDsp(Module *module) { cell->setParam(ID(USE_SIMD), Const("ONE48")); cell->setParam(ID(USE_DPORT), Const("FALSE")); - cell->setPort(ID(D), Const(0, 24)); + cell->setPort(ID(D), Const(0, 25)); cell->setPort(ID(INMODE), Const(0, 5)); cell->setPort(ID(ALUMODE), Const(0, 4)); cell->setPort(ID(OPMODE), Const(0, 7)); |