Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp

2 files changed, 30 insertions, 8 deletions

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index f6ae3a13f..45d7a34df 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -224,11 +224,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	pm.autoremove(st.ffH);
 	pm.autoremove(st.addAB);
 	if (st.ffO_lo) {
-			SigSpec O = st.sigO.extract(0,16);
+			SigSpec O = st.sigO.extract(0,st.ffO_lo->getParam("\\WIDTH").as_int());
 			st.ffO_lo->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
 	}
 	if (st.ffO_hi) {
-			SigSpec O = st.sigO.extract(16,16);
+			SigSpec O = st.sigO.extract(16,st.ffO_hi->getParam("\\WIDTH").as_int());
 			st.ffO_hi->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
 	}
 }
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index b6da1d2f6..8b1ac2563 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -23,6 +23,10 @@ code sigA clock clock_pol
 	sigA = port(mul, \A);
 
 	if (ffA) {
+        for (auto b : port(ffA, \Q))
+            if (b.wire->get_bool_attribute(\keep))
+                reject;
+
 		clock = port(ffA, \CLK).as_bit();
 		clock_pol = param(ffA, \CLK_POLARITY).as_bool();
 
@@ -41,6 +45,10 @@ code sigB clock clock_pol
 	sigB = port(mul, \B);
 
 	if (ffB) {
+        for (auto b : port(ffB, \Q))
+            if (b.wire->get_bool_attribute(\keep))
+                reject;
+
 		SigBit c = port(ffB, \CLK).as_bit();
 		bool cp = param(ffB, \CLK_POLARITY).as_bool();
 
@@ -67,6 +75,10 @@ code sigH sigO clock clock_pol
 
 	if (ffH) {
 		sigH = port(ffH, \Q);
+        for (auto b : sigH)
+            if (b.wire->get_bool_attribute(\keep))
+                reject;
+
 		sigO = sigH;
 
 		SigBit c = port(ffH, \CLK).as_bit();
@@ -144,21 +156,27 @@ endcode
 
 match ffO_lo
 	select ffO_lo->type.in($dff)
-	filter nusers(sigO.extract(0,16)) == 2
-	filter includes(port(ffO_lo, \D).to_sigbit_set(), sigO.extract(0,16).to_sigbit_set())
+	filter GetSize(sigO) >= param(ffO_lo, \WIDTH).as_int()
+	filter nusers(sigO.extract(0,param(ffO_lo, \WIDTH).as_int())) == 2
+	filter includes(port(ffO_lo, \D).to_sigbit_set(), sigO.extract(0,param(ffO_lo, \WIDTH).as_int()).to_sigbit_set())
 	optional
 endmatch
 
 match ffO_hi
 	select ffO_hi->type.in($dff)
-	filter nusers(sigO.extract(16,16)) == 2
-	filter includes(port(ffO_hi, \D).to_sigbit_set(), sigO.extract(16,16).to_sigbit_set())
+	filter GetSize(sigO) >= 16+param(ffO_hi, \WIDTH).as_int()
+	filter nusers(sigO.extract(16,param(ffO_hi, \WIDTH).as_int())) == 2
+	filter includes(port(ffO_hi, \D).to_sigbit_set(), sigO.extract(16,param(ffO_hi, \WIDTH).as_int()).to_sigbit_set())
 	optional
 endmatch
 
 code clock clock_pol sigO sigCD
 	if (ffO_lo || ffO_hi) {
 		if (ffO_lo) {
+            for (auto b : port(ffO_lo, \Q))
+                if (b.wire->get_bool_attribute(\keep))
+                    reject;
+
 			SigBit c = port(ffO_lo, \CLK).as_bit();
 			bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
 
@@ -168,11 +186,15 @@ code clock clock_pol sigO sigCD
 			clock = c;
 			clock_pol = cp;
 
-			if (port(ffO_lo, \Q) != sigO.extract(0,16))
+			if (port(ffO_lo, \Q) != sigO.extract(0,param(ffO_lo, \WIDTH).as_int()))
 				sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
 		}
 
 		if (ffO_hi) {
+            for (auto b : port(ffO_hi, \Q))
+                if (b.wire->get_bool_attribute(\keep))
+                    reject;
+
 			SigBit c = port(ffO_hi, \CLK).as_bit();
 			bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
 
@@ -182,7 +204,7 @@ code clock clock_pol sigO sigCD
 			clock = c;
 			clock_pol = cp;
 
-			if (port(ffO_hi, \Q) != sigO.extract(16,16))
+			if (port(ffO_hi, \Q) != sigO.extract(16,param(ffO_hi, \WIDTH).as_int()))
 				sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
 		}