Use C++11 final/override keywords.

6 files changed, 12 insertions, 12 deletions

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index f16cc4a0b..fff04074b 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -275,7 +275,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 struct Ice40DspPass : public Pass {
 	Ice40DspPass() : Pass("ice40_dsp", "iCE40: map multipliers") { }
-	void help() YS_OVERRIDE
+	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -294,7 +294,7 @@ struct Ice40DspPass : public Pass {
 		log("the accumulator to an arbitrary value can be inferred to use the {C,D} input.\n");
 		log("\n");
 	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing ICE40_DSP pass (map multipliers).\n");
 
diff --git a/passes/pmgen/ice40_wrapcarry.cc b/passes/pmgen/ice40_wrapcarry.cc
index 97d2008c2..e234906ad 100644
--- a/passes/pmgen/ice40_wrapcarry.cc
+++ b/passes/pmgen/ice40_wrapcarry.cc
@@ -72,7 +72,7 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
 
 struct Ice40WrapCarryPass : public Pass {
 	Ice40WrapCarryPass() : Pass("ice40_wrapcarry", "iCE40: wrap carries") { }
-	void help() YS_OVERRIDE
+	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -91,7 +91,7 @@ struct Ice40WrapCarryPass : public Pass {
 		log("        including restoring their attributes.\n");
 		log("\n");
 	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		bool unwrap = false;
 
diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc
index 4379ce1e6..c16b4486d 100644
--- a/passes/pmgen/peepopt.cc
+++ b/passes/pmgen/peepopt.cc
@@ -32,7 +32,7 @@ pool<SigBit> rminitbits;
 
 struct PeepoptPass : public Pass {
 	PeepoptPass() : Pass("peepopt", "collection of peephole optimizers") { }
-	void help() YS_OVERRIDE
+	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -41,7 +41,7 @@ struct PeepoptPass : public Pass {
 		log("This pass applies a collection of peephole optimizers to the current design.\n");
 		log("\n");
 	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		std::string genmode;
 
diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc
index 9cfad03ef..7b2938ddf 100644
--- a/passes/pmgen/test_pmgen.cc
+++ b/passes/pmgen/test_pmgen.cc
@@ -118,7 +118,7 @@ void opt_eqpmux(test_pmgen_pm &pm)
 
 struct TestPmgenPass : public Pass {
 	TestPmgenPass() : Pass("test_pmgen", "test pass for pmgen") { }
-	void help() YS_OVERRIDE
+	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -239,7 +239,7 @@ struct TestPmgenPass : public Pass {
 		log_cmd_error("Unknown pattern: %s\n", pattern.c_str());
 	}
 
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		if (GetSize(args) > 1)
 		{
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index f1f4b4206..d05157270 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -744,7 +744,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
 
 struct XilinxDspPass : public Pass {
 	XilinxDspPass() : Pass("xilinx_dsp", "Xilinx: pack resources into DSPs") { }
-	void help() YS_OVERRIDE
+	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -785,7 +785,7 @@ struct XilinxDspPass : public Pass {
 		log("        default: xc7\n");
 		log("\n");
 	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing XILINX_DSP pass (pack resources into DSPs).\n");
 
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
index b99653fb3..1410850c7 100644
--- a/passes/pmgen/xilinx_srl.cc
+++ b/passes/pmgen/xilinx_srl.cc
@@ -188,7 +188,7 @@ void run_variable(xilinx_srl_pm &pm)
 
 struct XilinxSrlPass : public Pass {
 	XilinxSrlPass() : Pass("xilinx_srl", "Xilinx shift register extraction") { }
-	void help() YS_OVERRIDE
+	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -212,7 +212,7 @@ struct XilinxSrlPass : public Pass {
 		log("\n");
 	}
 
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n");