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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 13:05:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 13:05:10 -0700 |
| commit | 5ce0c31d0e01603264b23cff8f6d431902f08b63 (patch) | |
| tree | f73865a3ede084fb0b1c2f343af06c8551aa725e /passes/pmgen | |
| parent | df53fe12e7ed667d36d3829681cfc43a3355b834 (diff) | |
| download | yosys-5ce0c31d0e01603264b23cff8f6d431902f08b63.tar.gz yosys-5ce0c31d0e01603264b23cff8f6d431902f08b63.tar.bz2 yosys-5ce0c31d0e01603264b23cff8f6d431902f08b63.zip | |
Add init support
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/xilinx_srl.cc | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index bfda55af0..7240c2fa3 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -42,20 +42,29 @@ void reduce_chain(xilinx_srl_pm &pm, int minlen) auto last_cell = ud.longest_chain.back(); + SigSpec initval; for (auto cell : ud.longest_chain) { log_debug(" %s\n", log_id(cell)); + SigBit Q = cell->getPort(ID(Q)); + log_assert(Q.wire); + auto it = Q.wire->attributes.find(ID(init)); + if (it != Q.wire->attributes.end()) { + initval.append(it->second[Q.offset]); + } + else + initval.append(State::Sx); if (cell != last_cell) pm.autoremove(cell); } Cell *c = last_cell; - SigSpec Q = st.first->getPort(ID(Q)); + SigBit Q = st.first->getPort(ID(Q)); c->setPort(ID(Q), Q); if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) { c->parameters.clear(); c->setParam(ID(DEPTH), GetSize(ud.longest_chain)); - // TODO c->setParam(ID(INIT), init); + c->setParam(ID(INIT), initval.as_const()); if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) c->setParam(ID(CLKPOL), 1); else |