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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-18 12:35:24 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-18 12:35:24 -0700 |
| commit | 44bf4ac35cf9f4fa81b8c9ae7f6e2f724e11934d (patch) | |
| tree | fd4ad34076375334ca4a5d61bbf817dbea900e9f /passes/pmgen | |
| parent | fd3b033903bf005c4308923ccb34ab269d55dd3e (diff) | |
| download | yosys-44bf4ac35cf9f4fa81b8c9ae7f6e2f724e11934d.tar.gz yosys-44bf4ac35cf9f4fa81b8c9ae7f6e2f724e11934d.tar.bz2 yosys-44bf4ac35cf9f4fa81b8c9ae7f6e2f724e11934d.zip | |
Add doc on pattern detector for overflow
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 8500a6072..5af48e4d2 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * 2019 Eddie Hung <eddie@fpgeh.com> * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -519,6 +520,10 @@ struct XilinxDspPass : public Pass { log("the add/subtract operator will cause those operations to be implemented using\n"); log("the 'SIMD' feature of DSPs.\n"); log("\n"); + log("Experimental feature: the presence of a `$ge' cell attached to the registered\n"); + log("P output implementing the operation \"(P >= <power-of-2>)\" will be transformed\n"); + log("into using the DSP48E1's pattern detector feature for overflow detection.\n"); + log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { |