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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 14:26:24 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 14:26:24 -0700 |
| commit | 1c7d721558737292a6e1c5492ac8032fcdd8e31e (patch) | |
| tree | 4b0e75cf42b4fe44db19dda6d852077d9b438002 /passes/pmgen | |
| parent | cab2bd083ed25ebe1113d5fd054df5983e5086e7 (diff) | |
| download | yosys-1c7d721558737292a6e1c5492ac8032fcdd8e31e.tar.gz yosys-1c7d721558737292a6e1c5492ac8032fcdd8e31e.tar.bz2 yosys-1c7d721558737292a6e1c5492ac8032fcdd8e31e.zip | |
Reject if not minlen from inside pattern matcher
Diffstat (limited to 'passes/pmgen')
| -rw-r--r-- | passes/pmgen/xilinx_srl.cc | 16 | ||||
| -rw-r--r-- | passes/pmgen/xilinx_srl.pmg | 3 |
2 files changed, 11 insertions, 8 deletions
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index 7240c2fa3..a4a893307 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -30,14 +30,11 @@ bool did_something; #include "passes/pmgen/ice40_dsp_pm.h" #include "passes/pmgen/peepopt_pm.h" -void reduce_chain(xilinx_srl_pm &pm, int minlen) +void reduce_chain(xilinx_srl_pm &pm) { auto &st = pm.st_reduce; auto &ud = pm.ud_reduce; - if (GetSize(ud.longest_chain) < minlen) - return; - log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type)); auto last_cell = ud.longest_chain.back(); @@ -115,9 +112,14 @@ struct XilinxSrlPass : public Pass { } extra_args(args, argidx, design); - auto f = std::bind(reduce_chain, std::placeholders::_1, minlen); - for (auto module : design->selected_modules()) - while (xilinx_srl_pm(module, module->selected_cells()).run_reduce(f)) {} + for (auto module : design->selected_modules()) { + bool did_something = false; + do { + auto pm = xilinx_srl_pm(module, module->selected_cells()); + pm.ud_reduce.minlen = minlen; + did_something = pm.run_reduce(reduce_chain); + } while (did_something); + } } } XilinxSrlPass; diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg index 69a9c7af2..3a2096653 100644 --- a/passes/pmgen/xilinx_srl.pmg +++ b/passes/pmgen/xilinx_srl.pmg @@ -2,6 +2,7 @@ pattern reduce udata <vector<Cell*>> chain longest_chain udata <pool<Cell*>> non_first_cells +udata <int> minlen code non_first_cells.clear(); @@ -38,7 +39,7 @@ code finally chain.pop_back(); log_assert(chain.empty()); - if (GetSize(longest_chain) > 1) + if (GetSize(longest_chain) >= minlen) accept; endcode |