Initial progress on xilinx_srl

3 files changed, 213 insertions, 0 deletions

diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index 382a1b4ad..479e03a56 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -30,3 +30,9 @@ PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg
 
 passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
 	$(P) mkdir -p passes/pmgen && python3 $< -o $@ -p peepopt $(filter-out $<,$^)
+
+# --------------------------------------
+
+OBJS += passes/pmgen/xilinx_srl.o
+passes/pmgen/xilinx_srl.o: passes/pmgen/xilinx_srl_pm.h
+$(eval $(call add_extra_objs,passes/pmgen/xilinx_srl_pm.h))
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
new file mode 100644
index 000000000..2d052534d
--- /dev/null
+++ b/passes/pmgen/xilinx_srl.cc
@@ -0,0 +1,115 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+// for peepopt_pm
+bool did_something;
+
+#include "passes/pmgen/xilinx_srl_pm.h"
+#include "passes/pmgen/ice40_dsp_pm.h"
+#include "passes/pmgen/peepopt_pm.h"
+
+void reduce_chain(xilinx_srl_pm &pm, int minlen)
+{
+	auto &st = pm.st_reduce;
+	auto &ud = pm.ud_reduce;
+
+	if (GetSize(ud.longest_chain) < minlen)
+		return;
+
+	log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
+
+	auto last_cell = ud.longest_chain.back();
+
+	for (auto cell : ud.longest_chain) {
+		log_debug("    %s\n", log_id(cell));
+		if (cell != last_cell)
+			pm.autoremove(cell);
+	}
+
+	Cell *c = last_cell;
+	SigSpec Q = st.first->getPort(ID(Q));
+	c->setPort(ID(Q), Q);
+
+	if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
+		c->parameters.clear();
+		c->setParam(ID(DEPTH), GetSize(ud.longest_chain));
+		// TODO c->setParam(ID(INIT), init);
+		if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+			c->setParam(ID(CLKPOL), 1);
+		else
+			log_abort();
+		if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
+			c->setParam(ID(ENPOL), 1);
+		else if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PN_)))
+			c->setParam(ID(ENPOL), 0);
+		else
+			c->setParam(ID(ENPOL), 2);
+		if (c->type.in(ID($_DFF_N_), ID($_DFF_P_)))
+			c->setPort(ID(E), State::S1);
+		c->setPort(ID(L), GetSize(ud.longest_chain)-1);
+		c->type = ID($__XILINX_SHREG_);
+	}
+	else
+		log_abort();
+
+	log("    -> %s (%s)\n", log_id(c), log_id(c->type));
+}
+
+struct XilinxSrlPass : public Pass {
+	XilinxSrlPass() : Pass("xilinx_srl", "Xilinx shift register extraction") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    xilinx_srl [options] [selection]\n");
+		log("\n");
+		log("TODO.\n");
+		log("\n");
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n");
+
+        int minlen = 3;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-minlen" && argidx+1 < args.size()) {
+				minlen = atoi(args[++argidx].c_str());
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+        auto f = std::bind(reduce_chain, std::placeholders::_1, minlen);
+		for (auto module : design->selected_modules())
+			while (xilinx_srl_pm(module, module->selected_cells()).run_reduce(f)) {}
+	}
+} XilinxSrlPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg
new file mode 100644
index 000000000..ae29ac6c9
--- /dev/null
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -0,0 +1,92 @@
+pattern reduce
+
+udata <vector<Cell*>> chain longest_chain
+udata <pool<Cell*>> non_first_cells
+
+code
+	non_first_cells.clear();
+	subpattern(setup);
+endcode
+
+match first
+	select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
+	filter !non_first_cells.count(first)
+//generate
+//	SigSpec A = module->addWire(NEW_ID);
+//	SigSpec B = module->addWire(NEW_ID);
+//	SigSpec Y = module->addWire(NEW_ID);
+//	switch (rng(3))
+//	{
+//	case 0:
+//		module->addAndGate(NEW_ID, A, B, Y);
+//		break;
+//	case 1:
+//		module->addOrGate(NEW_ID, A, B, Y);
+//		break;
+//	case 2:
+//		module->addXorGate(NEW_ID, A, B, Y);
+//		break;
+//	}
+endmatch
+
+code
+	longest_chain.clear();
+	chain.push_back(first);
+	subpattern(tail);
+finally
+	chain.pop_back();
+	log_assert(chain.empty());
+	if (GetSize(longest_chain) > 1)
+		accept;
+endcode
+
+// ------------------------------------------------------------------
+
+subpattern setup
+
+match first
+	select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
+endmatch
+
+match next
+	select nusers(port(next, \Q)) == 2
+	select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
+	index <IdString> next->type === first->type
+	index <SigSpec> port(next, \Q) === port(first, \D)
+endmatch
+
+code
+	non_first_cells.insert(next);
+endcode
+
+// ------------------------------------------------------------------
+
+subpattern tail
+arg first
+
+match next
+	semioptional
+	select nusers(port(next, \Q)) == 2
+	select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
+	index <IdString> next->type === chain.back()->type
+	index <SigSpec> port(next, \Q) === port(chain.back(), \D)
+//generate 10
+//	SigSpec A = module->addWire(NEW_ID);
+//	SigSpec B = module->addWire(NEW_ID);
+//	SigSpec Y = port(chain.back().first, chain.back().second);
+//	Cell *c = module->addAndGate(NEW_ID, A, B, Y);
+//	c->type = chain.back().first->type;
+endmatch
+
+code
+	if (next) {
+		chain.push_back(next);
+		subpattern(tail);
+	} else {
+		if (GetSize(chain) > GetSize(longest_chain))
+			longest_chain = chain;
+	}
+finally
+	if (next)
+		chain.pop_back();
+endcode