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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-22 12:02:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-22 12:02:30 -0700 |
| commit | 7f33a0294b7e6a299033cb4ee19bd86317737c08 (patch) | |
| tree | ca0b9b1fcd28775c828c7be8dda1aec3d2ca97f7 /passes/pmgen/xilinx_dsp_CREG.pmg | |
| parent | db27f2f3786fa867bf7524aff6a5b72c89932620 (diff) | |
| download | yosys-7f33a0294b7e6a299033cb4ee19bd86317737c08.tar.gz yosys-7f33a0294b7e6a299033cb4ee19bd86317737c08.tar.bz2 yosys-7f33a0294b7e6a299033cb4ee19bd86317737c08.zip | |
Cleanup use of hard-coded default parameters in light of #1945
Diffstat (limited to 'passes/pmgen/xilinx_dsp_CREG.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp_CREG.pmg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index b20e4f458..42d4d1b9b 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -42,7 +42,7 @@ udata <bool> dffcepol dffrstpol // and (b) uses the 'C' port match dsp select dsp->type.in(\DSP48A, \DSP48A1, \DSP48E1) - select param(dsp, \CREG, 1).as_int() == 0 + select param(dsp, \CREG).as_int() == 0 select nusers(port(dsp, \C, SigSpec())) > 1 endmatch @@ -61,7 +61,7 @@ code sigC sigP clock SigSpec P = port(dsp, \P); if (!dsp->type.in(\DSP48E1) || - param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") { + param(dsp, \USE_MULT).decode_string() == "MULTIPLY") { // Only care about those bits that are used int i; for (i = GetSize(P)-1; i >= 0; i--) |