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| author | Marcin Kościelnicki <marcin@symbioticeda.com> | 2019-11-18 08:19:53 +0100 |
|---|---|---|
| committer | Marcin Kościelnicki <mwk@0x04.net> | 2019-11-19 08:57:39 +0100 |
| commit | 15232a48af60fb7da3c3afdd144882ace2194197 (patch) | |
| tree | 9f65f4cf436dd53d1d926ae2bbd85c36433a70ed /passes/pmgen/xilinx_dsp_CREG.pmg | |
| parent | 7a9081440c33af05cd5b24b4eb8907ac2ba4876a (diff) | |
| download | yosys-15232a48af60fb7da3c3afdd144882ace2194197.tar.gz yosys-15232a48af60fb7da3c3afdd144882ace2194197.tar.bz2 yosys-15232a48af60fb7da3c3afdd144882ace2194197.zip | |
Fix #1462, #1480.
Diffstat (limited to 'passes/pmgen/xilinx_dsp_CREG.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp_CREG.pmg | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index a57043009..5cd34162e 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -63,12 +63,12 @@ code sigC sigP clock if (param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") { // Only care about those bits that are used int i; - for (i = 0; i < GetSize(P); i++) { - if (nusers(P[i]) <= 1) + for (i = GetSize(P)-1; i >= 0; i--) + if (nusers(P[i]) > 1) break; - sigP.append(P[i]); - } + i++; log_assert(nusers(P.extract_end(i)) <= 1); + sigP = P.extract(0, i); } else sigP = P; |