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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-17 16:06:20 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-17 16:06:20 -0800 |
| commit | e17f3f8c63603746ad3aa33e9900d91e9b86db39 (patch) | |
| tree | 4f995db7a34b71da33d9626df72ab4a3c97b3122 /passes/pmgen/xilinx_dsp.pmg | |
| parent | ee500b6d8e7a6cd10a8187a3fc69b46f3d155a91 (diff) | |
| download | yosys-e17f3f8c63603746ad3aa33e9900d91e9b86db39.tar.gz yosys-e17f3f8c63603746ad3aa33e9900d91e9b86db39.tar.bz2 yosys-e17f3f8c63603746ad3aa33e9900d91e9b86db39.zip | |
Consistency
Diffstat (limited to 'passes/pmgen/xilinx_dsp.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index b9a4b0864..20925c0dc 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -460,7 +460,7 @@ arg argD argQ clock code dff = nullptr; - if (GetSize(argQ) == 0) + if (argQ.empty() == 0) reject; for (const auto &c : argQ.chunks()) { // Abandon matches when 'Q' is a constant |