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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-10 21:33:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-10 21:33:14 -0700 |
| commit | b08797da6bf0061073dc662441e03b2fd218f11f (patch) | |
| tree | 0a938cd6e4b6f517fca2faa6412c03408b603683 /passes/pmgen/xilinx_dsp.pmg | |
| parent | 37a34eeb0438261f432917fb5d60a5320f56a8de (diff) | |
| download | yosys-b08797da6bf0061073dc662441e03b2fd218f11f.tar.gz yosys-b08797da6bf0061073dc662441e03b2fd218f11f.tar.bz2 yosys-b08797da6bf0061073dc662441e03b2fd218f11f.zip | |
Only pack out registers if \init is zero or x; then remove \init from PREG
Diffstat (limited to 'passes/pmgen/xilinx_dsp.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 05837d057..7db8e95a6 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -290,8 +290,8 @@ endmatch code argQ if (ff) { - for (auto b : argQ) - if (b.wire->get_bool_attribute(\keep)) + for (auto c : argQ.chunks()) + if (c.wire->get_bool_attribute(\keep)) reject; if (clock != SigBit()) { @@ -447,9 +447,13 @@ code if (dff) { dffQ = port(dff, \Q); - for (auto b : dffQ) - if (b.wire->get_bool_attribute(\keep)) + for (auto c : dffQ.chunks()) { + if (c.wire->get_bool_attribute(\keep)) reject; + Const init = c.wire->attributes.at(\init, State::Sx); + if (!init.is_fully_undef() && !init.is_fully_zero()) + reject; + } if (clock != SigBit()) { if (port(dff, \CLK) != clock) |