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authorEddie Hung <eddie@fpgeh.com>2020-04-22 12:02:30 -0700
committerEddie Hung <eddie@fpgeh.com>2020-04-22 12:02:30 -0700
commit7f33a0294b7e6a299033cb4ee19bd86317737c08 (patch)
treeca0b9b1fcd28775c828c7be8dda1aec3d2ca97f7 /passes/pmgen/xilinx_dsp.pmg
parentdb27f2f3786fa867bf7524aff6a5b72c89932620 (diff)
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Cleanup use of hard-coded default parameters in light of #1945
Diffstat (limited to 'passes/pmgen/xilinx_dsp.pmg')
-rw-r--r--passes/pmgen/xilinx_dsp.pmg18
1 files changed, 9 insertions, 9 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index af47ab111..d40f073c9 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -95,7 +95,7 @@ code sigA sigB sigC sigD sigM clock
sigD = port(dsp, \D, SigSpec());
SigSpec P = port(dsp, \P);
- if (param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") {
+ if (param(dsp, \USE_MULT).decode_string() == "MULTIPLY") {
// Only care about those bits that are used
int i;
for (i = GetSize(P)-1; i >= 0; i--)
@@ -120,7 +120,7 @@ endcode
// reset functionality, using a subpattern discussed above)
// If matched, treat 'A' input as input of ADREG
code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock
- if (param(dsp, \ADREG, 1).as_int() == 0) {
+ if (param(dsp, \ADREG).as_int() == 0) {
argQ = sigA;
subpattern(in_dffe);
if (dff) {
@@ -144,7 +144,7 @@ endcode
match preAdd
if sigD.empty() || sigD.is_fully_zero()
// Ensure that preAdder not already used
- if param(dsp, \USE_DPORT, Const("FALSE")).decode_string() == "FALSE"
+ if param(dsp, \USE_DPORT).decode_string() == "FALSE"
if port(dsp, \INMODE, Const(0, 5)).is_fully_zero()
select preAdd->type.in($add)
@@ -176,7 +176,7 @@ code argQ ffAD ffADcemux ffADrstmux ffADcepol ffADrstpol sigA clock ffA2 ffA2cem
// Only search for ffA2 if there was a pre-adder
// (otherwise ffA2 would have been matched as ffAD)
if (preAdd) {
- if (param(dsp, \AREG, 1).as_int() == 0) {
+ if (param(dsp, \AREG).as_int() == 0) {
argQ = sigA;
subpattern(in_dffe);
if (dff) {
@@ -237,7 +237,7 @@ endcode
// (5) Match 'B' input for B2REG
// If B2REG, then match 'B' input for B1REG
code argQ ffB2 ffB2cemux ffB2rstmux ffB2cepol ffBrstpol sigB clock ffB1 ffB1cemux ffB1rstmux ffB1cepol
- if (param(dsp, \BREG, 1).as_int() == 0) {
+ if (param(dsp, \BREG).as_int() == 0) {
argQ = sigB;
subpattern(in_dffe);
if (dff) {
@@ -287,7 +287,7 @@ endcode
// (6) Match 'D' input for DREG
code argQ ffD ffDcemux ffDrstmux ffDcepol ffDrstpol sigD clock
- if (param(dsp, \DREG, 1).as_int() == 0) {
+ if (param(dsp, \DREG).as_int() == 0) {
argQ = sigD;
subpattern(in_dffe);
if (dff) {
@@ -308,7 +308,7 @@ endcode
// (7) Match 'P' output that exclusively drives an MREG
code argD ffM ffMcemux ffMrstmux ffMcepol ffMrstpol sigM sigP clock
- if (param(dsp, \MREG, 1).as_int() == 0 && nusers(sigM) == 2) {
+ if (param(dsp, \MREG).as_int() == 0 && nusers(sigM) == 2) {
argD = sigM;
subpattern(out_dffe);
if (dff) {
@@ -363,7 +363,7 @@ endcode
// (9) Match 'P' output that exclusively drives a PREG
code argD ffP ffPcemux ffPrstmux ffPcepol ffPrstpol sigP clock
- if (param(dsp, \PREG, 1).as_int() == 0) {
+ if (param(dsp, \PREG).as_int() == 0) {
int users = 2;
// If ffMcemux and no postAdd new-value net must have three users: ffMcemux, ffM and ffPcemux
if (ffMcemux && !postAdd) users++;
@@ -424,7 +424,7 @@ endcode
// to implement this function
match overflow
if ffP
- if param(dsp, \USE_PATTERN_DETECT, Const("NO_PATDET")).decode_string() == "NO_PATDET"
+ if param(dsp, \USE_PATTERN_DETECT).decode_string() == "NO_PATDET"
select overflow->type.in($ge)
select GetSize(port(overflow, \Y)) <= 48
select port(overflow, \B).is_fully_const()