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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 12:43:56 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 22:31:04 -0700 |
| commit | 7de9c33931020068b285e262bbf239385fcb5c2d (patch) | |
| tree | 7b46e853474ce4c3b1cccc0eb321cb1a611aa400 /passes/pmgen/xilinx_dsp.pmg | |
| parent | 983068103e24c33a1b70eb90dd72fdfaf292e1bd (diff) | |
| download | yosys-7de9c33931020068b285e262bbf239385fcb5c2d.tar.gz yosys-7de9c33931020068b285e262bbf239385fcb5c2d.tar.bz2 yosys-7de9c33931020068b285e262bbf239385fcb5c2d.zip | |
Fix TODOs
Diffstat (limited to 'passes/pmgen/xilinx_dsp.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index bcf966a8a..6b6151564 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -103,11 +103,6 @@ code sigA sigB sigC sigD sigM clock } else sigM = P; - // TODO: Check if necessary - // This sigM could have no users if downstream $add - // is narrower than $mul result, for example - if (sigM.empty()) - reject; clock = port(dsp, \CLK, SigBit()); endcode @@ -159,16 +154,6 @@ match preAdd optional endmatch -code sigA sigD - // TODO: Check if this is necessary? - if (preAdd) { - sigA = port(preAdd, \A); - sigD = port(preAdd, \B); - if (GetSize(sigA) < GetSize(sigD)) - std::swap(sigA, sigD); - } -endcode - // (4) If pre-adder was present, find match 'A' input for A2REG // If pre-adder was not present, move ADREG to A2REG // Then match 'A' input for A1REG |